/*
 * usb_defins.h
 *
 *  Created on: 11.03.2012
 *      Author: g.kruglov
 */

#ifndef USB_DEFINS_H_
#define USB_DEFINS_H_

#define RegBase  (0x40005C00L)  /* USB_IP Peripheral Registers base address */
#define PMAAddr  (0x40006000L)  /* USB_IP Packet Memory Area base address   */

/******************************************************************************/
/*                         General registers                                  */
/******************************************************************************/
#define CNTR    ((__IO unsigned *)(RegBase + 0x40))     // Control register
#define ISTR    ((__IO unsigned *)(RegBase + 0x44))     // Interrupt status register
#define FNR     ((__IO unsigned *)(RegBase + 0x48))     // Frame number register
#define DADDR   ((__IO unsigned *)(RegBase + 0x4C))     // Device address register
#define BTABLE  ((__IO unsigned *)(RegBase + 0x50))     // Buffer Table address register

/******************************************************************************/
/*             CNTR control register bits definitions                         */
/******************************************************************************/
#define CNTR_CTRM   (0x8000) /* Correct TRansfer Mask */
#define CNTR_DOVRM  (0x4000) /* DMA OVeR/underrun Mask */
#define CNTR_ERRM   (0x2000) /* ERRor Mask */
#define CNTR_WKUPM  (0x1000) /* WaKe UP Mask */
#define CNTR_SUSPM  (0x0800) /* SUSPend Mask */
#define CNTR_RESETM (0x0400) /* RESET Mask   */
#define CNTR_SOFM   (0x0200) /* Start Of Frame Mask */
#define CNTR_ESOFM  (0x0100) /* Expected Start Of Frame Mask */

#define CNTR_RESUME (0x0010) /* RESUME request */
#define CNTR_FSUSP  (0x0008) /* Force SUSPend */
#define CNTR_LPMODE (0x0004) /* Low-power MODE */
#define CNTR_PDWN   (0x0002) /* Power DoWN */
#define CNTR_FRES   ((uint16_t)0x0001) /* Force USB RESet */

/******************************************************************************/
/*                       ISTR interrupt events                                */
/******************************************************************************/
#define ISTR_CTR    (0x8000) /* Correct TRansfer (clear-only bit) */
#define ISTR_DOVR   (0x4000) /* DMA OVeR/underrun (clear-only bit) */
#define ISTR_ERR    (0x2000) /* ERRor (clear-only bit) */
#define ISTR_WKUP   (0x1000) /* WaKe UP (clear-only bit) */
#define ISTR_SUSP   (0x0800) /* SUSPend (clear-only bit) */
#define ISTR_RESET  (0x0400) /* RESET (clear-only bit) */
#define ISTR_SOF    (0x0200) /* Start Of Frame (clear-only bit) */
#define ISTR_ESOF   (0x0100) /* Expected Start Of Frame (clear-only bit) */

#define ISTR_DIR    (0x0010)  /* DIRection of transaction (read-only bit)  */
#define ISTR_EP_ID  (0x000F)  /* EndPoint IDentifier (read-only bit)  */

#define CLR_CTR    (uint16_t)(~ISTR_CTR)   /* clear Correct TRansfer bit */
#define CLR_DOVR   (uint16_t)(~ISTR_DOVR)  /* clear DMA OVeR/underrun bit*/
#define CLR_ERR    (uint16_t)(~ISTR_ERR)   /* clear ERRor bit */
#define CLR_WKUP   (uint16_t)(~ISTR_WKUP)  /* clear WaKe UP bit     */
#define CLR_SUSP   (uint16_t)(~ISTR_SUSP)  /* clear SUSPend bit     */
#define CLR_RESET  (uint16_t)(~ISTR_RESET) /* clear RESET bit      */
#define CLR_SOF    (uint16_t)(~ISTR_SOF)   /* clear Start Of Frame bit   */
#define CLR_ESOF   (uint16_t)(~ISTR_ESOF)  /* clear Expected Start Of Frame bit */

/******************************************************************************/
/*               DADDR Device ADDRess bit definitions                         */
/******************************************************************************/
#define DADDR_EF (0x80)
#define DADDR_ADD (0x7F)

/******************************************************************************/
/*                         Endpoint registers                                 */
/******************************************************************************/
#define pEPRxAddr(bEpNum)  ((uint32_t *)((*BTABLE + bEpNum*8+4)*2 + PMAAddr))
#define pEPTxAddr(bEpNum)  ((uint32_t *)((*BTABLE + bEpNum*8  )*2 + PMAAddr))
#define pEPTxCount(bEpNum) ((uint32_t *)((*BTABLE + bEpNum*8+2)*2 + PMAAddr))
#define pEPRxCount(bEpNum) ((uint32_t *)((*BTABLE + bEpNum*8+6)*2 + PMAAddr))


#define EP0REG  ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */

/******************************************************************************/
/*                            Endpoint register                               */
/******************************************************************************/
/* bit positions */
#define EP_CTR_RX      (0x8000) /* EndPoint Correct TRansfer RX */
#define EP_DTOG_RX     (0x4000) /* EndPoint Data TOGGLE RX */
#define EPRX_STAT      (0x3000) /* EndPoint RX STATus bit field */
#define EP_SETUP       (0x0800) /* EndPoint SETUP */
#define EP_T_FIELD     (0x0600) /* EndPoint TYPE */
#define EP_KIND        (0x0100) /* EndPoint KIND */
#define EP_CTR_TX      (0x0080) /* EndPoint Correct TRansfer TX */
#define EP_DTOG_TX     (0x0040) /* EndPoint Data TOGGLE TX */
#define EPTX_STAT      (0x0030) /* EndPoint TX STATus bit field */
#define EPADDR_FIELD   (0x000F) /* EndPoint ADDRess FIELD */

/* EndPoint REGister MASK (no toggle fields) */
#define EPREG_MASK     (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD)

/* EP_TYPE[1:0] EndPoint TYPE */
#define EP_TYPE_MASK   (0x0600) /* EndPoint TYPE Mask */
#define EP_BULK        (0x0000) /* EndPoint BULK */
#define EP_CONTROL     (0x0200) /* EndPoint CONTROL */
#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
#define EP_INTERRUPT   (0x0600) /* EndPoint INTERRUPT */
#define EP_T_MASK      (~EP_T_FIELD & EPREG_MASK)


/* EP_KIND EndPoint KIND */
#define EPKIND_MASK    (~EP_KIND & EPREG_MASK)

/* STAT_TX[1:0] STATus for TX transfer */
#define EPTX_DTOGMASK  (EPTX_STAT|EPREG_MASK)

/* STAT_RX[1:0] STATus for RX transfer */
#define EPRX_DTOGMASK  (EPRX_STAT|EPREG_MASK)

// ============================ USB request ====================================
#define REQ_DIR_MASK    0x80
#define REQ_TYPE_MASK   0x60
#define REQ_RECIP_MASK  0x1F


#endif /* USB_DEFINS_H_ */
